Floating gate memory device includes a charge trap region, wherein charges are stored in an isolated conductor, commonly referred to as a floating gate, in a field-effect transistor (FET) device. A memory cell operates by storing electric charge (representing either a binary “1” or “0” state of one data bit) on the floating gate, which is incorporated into a MOS (Metal-Oxide Semiconductor) field-effect transistor. The stored charges affect the threshold voltage (VT) of the transistor, thereby providing a way to read the current through the storage device.
A memory cell typically consists of a transistor, a floating gate, and a control gate above the floating gate in a stacked gate structure. The floating gate, typically composed of polycrystalline silicon (i.e., “polysilicon”), is electrically isolated from the underlying semiconductor substrate by a thin dielectric layer, which is typically formed of an insulating oxide, and more particularly, silicon oxide. This dielectric layer is often referred to as a tunnel oxide layer. The control gate is positioned above the floating gate, and is electrically isolated from the floating gate by a storage dielectric layer. Thus, the floating gate serves as a charge trap region, wherein charges are stored in the charge trap region. Other charge storage devices are constructed to store charges in insulator bulk traps in the FET device, such as MNOS (metal-nitride-oxide-semiconductor), MAOS (metal-alumina-oxide-semiconductor), MAS (metal-alumina-semiconductor), and SONOS (silicon-oxide-nitride-oxide-semiconductor) memory cells.
A programmed memory cell has its VT increased by increasing the amount of negative charge stored on the floating gate, i.e., for given source and drain voltages, the control gate voltage which allows a current to flow between the source and the drain of a programmed memory cell is higher than that of a non-programmed memory cell. Therefore, the state of a memory cell is read by applying a control gate voltage below the predetermined level corresponding to the programmed state, but sufficiently high to allow a current between the source and the drain in a non-programmed memory cell. If a current is detected, then the memory cell is read to be not programmed.
The floating gate memory, such as flash memory, can configure very high density memory. Then, the flash memory is applied to the memory of BIOS (basic I/O system) in the computer system, the memory of the communication rule etc. in a portable telephone, and the memory of the image in the digital camera, etc. as substitution of the hard disk drive.
The conventional flash memory is realized by using the sense amp in order to measure the current of the floating gate transistor. In FIG. 1A, one of prior arts for the sense amp is illustrated, as published, U.S. Pat. No. 5,973,957. The function of the sense amplifier 108, or comparator, is to make a comparison of the cell being sensed 102 to a reference cell 104. This comparison is accomplished by passing the cell current through a load device 106 which converts the current to a voltage. The load device 106 is an S-device in one embodiment, but is not so limited; for example, the load device 106 may be a p-channel device having a grounded gate or a resistor. The S-device is a high trans-conductance n-channel transistor that is specially doped to provide a threshold voltage that is lower than the threshold voltage of a standard n-channel CMOS device. For one embodiment, the S-device is doped to have a threshold voltage of approximately 0.3 volts. The sense amplifier 108, or comparator, then compares the threshold voltage Vt 104 from a reference cell to the voltage of the flash cell 102 and provides an output 110 based on the results of the comparison. The load device 112 of the reference cell, for one embodiment, is the same type of device as the load device 106 or the flash cell.
In FIG. 1B, another prior art is illustrated for reading the stored data with bipolar transistor as published, U.S. Pat. No. 5,978,264, wherein a bipolar transistor 163 serves as an amplify device. During read operation, the bipolar transistor amplifies cell current flow of a p-type floating gate memory cell 152, and the emitter and the base of the bipolar transistor 163 are controlled by a PMOS transfer transistor 161, to be shorted. And the base 162 of the bipolar transistor is connected to sub bit line 154 through PMOS transfer transistor 155, the selected memory cell 152 is connected sub bit line, word line 151 is asserted to the memory cell and source line 153 sinks the cell current when low threshold data is stored in the selected memory cell. Thus, the bipolar transistor changes the main bit line 164. Otherwise, the bipolar transistor 163 is floating, because the cell transistor is turned off when read high threshold data. However, the gain is limited because the collector current is amplified by the base current.
The conventional flash memory has progressed its miniaturization and as a result there arises difficulties in obtaining necessary current to measure the stored data in the memory cell. The turn-on current of the cell transistor should drive the selected bit line where the bit line loading is relatively high because multiple memory cells are connected to a bit line. Also unselected memory cells flow leakage current, which discharges the selected bit line. Thus, the ratio between the turn-on current and the turn-off current should be relatively high to differentiate low threshold data and high threshold data, such as several 1000 times different. When the ratio is very low, the comparator can not differentiate low threshold data and high threshold data because the leakage current (turn-off current) also discharge the bit line, which may cause the sensing error.
Furthermore, one of major problem is that the turn-on current through the floating gate MOS transistor is low, around 10 uA or less for the conventional flash memory, as published, “New Self-Adjusted Dynamic Source Multilevel P-Channel Flash Memory”, IEEE Transactions Electron Devices”, Vol. 47 No. 4 pp. 841-847, April 2000. Even worse in the other types of floating gate memory, such as the nanocrystal memory, the drain current of the memory cell is around 1 nA or less, as published, “Metal Nanocrystal Memories—Part II: Electrical Characteristics”, IEEE Transactions on Electron Devices, Vol. 49, No. 9, September, 2002. And for the single electron memory (SEM) including quantum dot, the drain current is 1.5 p˜3 pA as published, “Room temperature Coulomb oscillation and memory effect for single electron memory made by pulse-mode AFM nano-oxidation process”, 0-7803-4774-9/98 16.6.2 IEDM 1998.
In this respect, there is still a need to improve the floating gate memory, in order to read the cell transistor more effectively, even though the cell transistor can flow relatively low current. In the present invention, multi-divided bit line architecture is introduced to reduce the parasitic capacitance of the bit line, and a segment read circuit is added for the multi-divided local bit line. And one more major improvement is that a time-domain sensing scheme is introduced in order to differentiate low threshold data and high threshold data.
And, the memory cell can be formed from single crystal silicon on the surface of a wafer. Alternatively, the memory cell can be formed from thin film polysilicon layer, because the lightly loaded bit line can be quickly discharged by the cell transistor even tough the thin film cell transistor can flow relatively low current. In doing so, multi-stacked NOR flash memory is realized with thin film cell transistor, which can increase the density of the flash memory within the conventional CMOS process with additional process steps, because the conventional planar CMOS process is reached to the scaling limit for fabricating cell transistors on the surface of the wafer.